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| INDEX MX98713A FAST ETHERNET MAC CONTROLLER 1. FEATURES * Integrates fast Ethernet MAC, NWAY, 100 Base-TX PCS and 10 Base-T tranceive in a single chip. * Fully comply to IEEE 802.3u specification * MII/SYM interface to support STP and CAT5 UTP cable. * Support full duplex operation in both 100 Base-TX and 10 Base-T mode. * Magic Packet TM mode to support remote wake up and remote power on. * On chip 100 Base-TX PCS and 10 Base-T transceiver with filter. * 100/10 Base-T NWAY auto negotiation function. * Large on chip FIFOs for both transmit and receive operations without external local memory * Fully comply to PCI spec. 2.1 with bus clock ranges from 16 MHz to 33 MHz. * PCI Bus master architecture with linked host buffers delivers excellent performance. * 32-bit bus master DMA channel provides ultra low CPU utilization. * Support up to 256K bytes boot ROM and FLASH interface * Two levels of loopback diagnositic capability * Support a variety of flexible address filtering modes with 16 CAM address and 512 bits hash. * MicroWire interface to EEPROM for customer's IDs and configuration data. * 160 PQFP package with CMOS technology, pin-to-pin compatible to MX98713 ( Magic Packet Technology is a trademark of Advanced Micro Device Corp. ) 2. GENERAL DESCRIPTION The MX98713A Fast Ethernet controller is designed to interface directly with PCI bus and 100/10 Base-T Fast Ethernet with MII/SYM interface and a 10 Base-T transceiver to support NWAY autonegotiation with any 100 Base-TX PHY/PMD chips. Together with MX98702 ( 100 Base-TX PMD ) and MX98704 ( 100 Base-TX PHY ), or with a MX98705 ( 100 Base-TX PHY/PMD combo ) chip creates a total solution for Fast Ethernet adaptor application. High speed PCI bus master interface with large on chip FIFOs, the MX98713A provides a cost effective solution that delivers excellent performance. Nway function enables user to plug in cable and link up the network automatically. Magic Packet based advanced power management not only save electric energy but also provides network maintenance efficiency through the application of Remote-Wake-Up and P/N:PM0489 REV. 1.0, AUG. 28, 1997 1 INDEX MX98713A Remote-Power-On. This feature is most valuable for high-end green PCs and intelligent LAN environment. Full duplex and half duplex are both supported. A packet buffer is located in the host memory that is used by MX98713As device driver for all incoming and outgoing packets. This buffer area is shared by both transmit process and receive process. During reception, the MX98713A stores packets in the receive buffer area, then indicates receive status and control information in the descriptor area. This packet buffer is also used by transmit process which can transmit multiple packets from a single transmit command. Back-to-back packets at full line speed in 100 Base-TX mode is effortless with MX98713A. 3. PIN CONFIGURATIONS FWE# GND PWD100# TEST INTA# RST# VDD GND CLK VDD GNT# REQ# GND AD31 AD30 GND AD29 AD28 GND AD27 AD26 VDD AD25 AD24 CBEB3 IDSEL GND AD23 AD22 AD21 AD20 VDD AD19 AD18 VDD GND GND AD17 AD16 GND 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 MX98713A 120 119 118 117 116 115 114 113 112 111 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 TXP VDD RXIP RXIM GND VDD MDC MDIO BPA0 FCS# BPA1 BPA2 BPD7 BPD6 VDD GND BPD5 BPD4 BPD3 BPD2 BPD1 BPD0 GND BPA3 BPA4 BPA5 BPA6 VDD GND BPA7 BPA8 BPA9 BPA10 EECS EECK EEDI EEDO VDD GND GND 2 INDEX MX98713A 4. PIN DESCRIPTION ( 160 PIN PQFP ) ( T/S : tri-state, S/T/S : sustended tri-state, I : input, O : output, O/D : open drain ) Pin Name Type 160 Pin Function and Driver PCI address/data bus: shared PCI address/data bus lines. Little or big endian byte ordering are supported. PCI command and byte enable bus: shared PCI command byte enable bus, during the address phase of the transaction, these four bits provide the bus command. During the data phase, these four bits provide the byte enable. PCI FRAME# signal: shared PCI cycle start signal, asserted to indicate the beginning of a bus transaction. While FRAMEB is asserted, data transfers continue. PCI Target ready: issued by the target agent, a data phase is completed on the rising edge of PCICLK when both IRDYB and TRDYB are asserted. PCI Master ready: indicates the bus master's ability to complete the current data phase of the transaction. A data phase is completed on any rising edge of PCICLK when both IRDYB and TRDYB are asserted. PCI slave device select: asserted by the target of the current bus access. When 98713A is the initiator of current bus access, the target must assert DEVSELB within 5 bus cycles, otherwise cycle is aborted. PCI initialization device select: target specific device select signal for configuration cycles issued by host PCI bus clock input: PCI bus clock targeted at 33MHZ PCI bus reset: host system hardware reset PCI bus interrupt request signal: wired to INTAB lines AD[31:0] I/O CBE[3:0] I/O FRAMEB I/O TRDYB I/O IRDYB I/O DEVSELB I/O IDSEL PCICLK PRSTB INTAB I I I O/D 3 INDEX MX98713A Pin Name Type 160 Pin Function and Driver PCI bus system error signal: If an address parity error is detected and CFCS bit 8 is enabled, SERR# and CFCS's bit 30 will be asserted. 6mA tristate driver PCI bus data error signal: As a bus master, when a data parity error is detected and CFCS bit 8 is enabled, CFCS bit 24 and CSR5 bit 13 will be asserted. As a bus target, a data parity error will cause PERR# to be asserted. PCI bus parity bit: shared PCI bus even parity bit for 32 bits AD bus and CBE bus. PCI Target requested transfer stop signal: as bus master, assertion of STOP# cause PMAC either to retry, disconnect, or abort. PCI bus request signal: to initiate a bus master cycle request PCI bus grant acknowledge signal: asserts to indicate to PMAC that access to the bus is granted TX activity indicator : diecrtly sink external LED circuit with a serial resistor of 270-330 Ohm. RX activity indicator: directly sink external LED cuircuit with a serial resistor of 270-330 ohm. Good Link/Signal detect indicator: diecrtly sink external LED circuit with a serial resistor, indicating good link in 10Base-T setup or Signal Detect Good in 100Base-TX setup. Boot PROM address bit 17:driven by MX98713A, together with BPA[17 :0] to access external boot PROM up to 256KB PHY device external loopback control: driven by MX98713A to force PHY device to do loopback. Boot PROM address bit 16: driven by MX98713A, together with BPA[17 :0] to access external boot PROM up to 256KB Boot PROM address bit 15: driven by MX98713A, together with BPA[17 :0] to access external boot PROM up to 256KB. SERRB I/O PERRB I/O PAR I/O STOPB REQB GNTB I/O O I TXLED RXLED O O GDLED O BPA17 LPBKB O O BPA16 O BPA15 O 4 INDEX MX98713A Pin Name BPA[14:0] MDC MDIO EECS EECK EEDI EEDO SD Type O O I/O O O O I I 160 Pin Function and Driver Boot RPOM address lines: driven by MX98713A, together with BPA15 can access external bootPROM up to 64KB. MII management interface clock: sourced by MX98713A MII management interface IO data bit: Net ID ROM chip select: Net ID ROM interface clock output: Net ID ROM input data bit: Net ID ROM output data bit: Signal detect indication: supplied by external PMD device. Collision detect of MII/SYM interface: sourced by external physical layer protocol ( PHY ) device. Carrier sense of MII/SYM interface: sourced by external physical layer protocol ( PHY ) device. Receive data valid signal of MII/SYM interface: asserted by external PHY when receive data is presented on MII_RXD lines. Receive error signal of MII/SYM interface: synchronous to MII_RXC and asserted by external PHY when a data decoding error occures COL I CRS I RXDV I RXER I 5 INDEX MX98713A Pin Name TXP Type O 160 Pin Function and Driver Twisted pair transmit differential output: Together with TXM provides 10 Base-T transmit differential output Twisted pair transmit differential output: Together with TXP provides 10 Base-T transmit differential output Bias control: A external resistor ( 12k ohms, 5% accuracy ) connects this pin to ground for operating bias control Crystal or external oscillator input: frequencies of 20Mhz, used by 10 Base-T interface. Crystal feedback output: Used in crystal connections only. Should be left completely unconnected when using an oscillator module. External 100 TX enable: set to disable external 100Base-TX transceiver, reset to enable external 100Base-TX transceiver, it can be used to drive external port LED. Power Down external 100 Base-TX PHY/PMD : Whenever Magic Packet mode or sleep mode is set, this pin goes low until a recovery event occur when this pin will be asserted high. It can be used to wake-up the host system. Configuration input bit 2: Should be unconnected for normal operation Configuration input bit 1: Should be unconnected for normal operation Flash Write Enable: Used in the boot ROM interface. Serial mode select: Together with SPDSEL pin defines 4 operation modes. See SPDSEL pin description for details. Bypass Scrambler mode: When set to low enables scrambler function and MII/SYM port transmits and receives scrambler symbols. When reset to bypass scrambler/descrambler function. . Flash Output Enable: Used in the boot ROM/Flash interface. TEST pin: Set high for test mode, normally grounded. TXM O RB I X1 I X2 O EN100B O PWD100B O CONF2 CONF1 FWEB SNSEL I I O I BPSCR I FOEB TEST O I 6 INDEX MX98713A Pin Name RXC Type I 160 Pin Function and Driver Receive clock of MII/SYM interface: supports either 25MHz or 2.5 MHz clock. Sourced by external PHY. Parallel Receive data lines: driven by external PHY and is synchronous to RXC clock. In MII mode, these are received 4 data lines. In PCS mode, combined with SYM_RXD4 forms 5 parallel data lines in symbol form. Received data line in SYM mode: MSB bit of received symbol data Transmit clock of MII/SYM interface: supports either 25MHz or 2.5 MHz clock. Sourced by external PHY. Parallel Transmit data lines: drievn by PMAC synchronously to TXC clock. Data is latched by external PHY at the rising edge of TXC. Transmit data line in PCS mode: together with MII/SYM_TXD[3:0] provide five parallel lines of data in symbol form in SYM mode. RXD[3:0] I RXD4 TXC I I TXD[3:0] O TXD4 O TXEN BPD[7:0] O I Transmit enable signal of MII/SYM interface: Boot ROM data lines: byte wide data bus Twisted pair receive differential input: together with RXIM provides 10 Base-T differential receive input. Twisted pair receive differential input: together with RXIP provides 10 Base-T receive differential input. RXIP I RXIM I 7 INDEX MX98713A 5. PROGRAMMING INTERFACE 5.1 PCI CONFIGURATION REGISTERS: 5.1.1 PCI ID REGISTER ( PFID ) ( Offset 03h-00h ) Device ID ( bit 31:16 ) Vendor ID ( bit15:0 ) This register can be loaded from external serial EEPROM or use a MXIC preset value of "10D9" and "0531" for vendor ID and device ID respectively. Word location 3Eh and 3Dh in serial EEPROM are used to configure customer's vendor ID and device ID respectively. If location 3Eh contains "FFFF" value then MXIC's vendor ID and device ID will be set in this register, otherwise both 3Eh and 3Dh will be loaded into this register from serial EEPROM. 5.1.2 PCI REVISION REGISTER ( PFRV ) ( Offset 0Bh-08h ) Base Class Subclass Revision Number Step Number bit 3 - 0 : Step Number, range from 0 to Fh. bit 7 - 4 : Revision Number, fixed to 1h for MX98713A bit 15 - 8 : not used bit 23 - 16 : Subclass, fixed to 0h. bit 31 - 24 : Base Class, fixed to 3h. 8 INDEX MX98713A 5.1.3 PCI LATENCY TIMER REGISTER ( PFLT ) (Offset 0Fh-0Ch) Configuration Latency Timer System cache line size bit 0 - bit 7 : System cache line size in units of 32 bit word, device driver should use this value to rogramCSR0<15:14>. bit 8 - bit 15 : Configuration Latency Timer, when MX98713A assert FRAME#, it enables its latency timer to count. If MX98713A deasserts FRAME# prior to timer expiration, then timer is ignored. Otherwise, after timer expires, MX98713A initiates trans action termination as soon as its GNT# is deasserted. 5.1.4 PCI BASE IO ADDRESS REGISTER ( PBIO ) ( Offset 13h-10h ) Configuration Base IO Address IO/Memory Space Indicator bit 0 : IO/Memory Space Indicator, fixed to 1 in this field will map into the IO space. This is a read only field. bit 7 - 1 : not used, all 0 when read bit 31 - 8 : Defines the address assignment mapping of MX98713A CSR registers. 9 INDEX MX98713A 5.1.5 PCI BASE MEMORY ADDRESS REGISTER ( PBMA ) ( Offset 17h-14h ) Configuration Base Memory Address Memory Space Indicator bit 0 : Memory Space Indicator, fixed to 0 in this field will map into the memory space. This is a read only field. bit 6 - 1 : not used, all 0 when read bit 31 - 7 : Defines the address assignment mapping of MX98713A CSR registers. 5.1.6 PCI BASE EXPANSION ROM ADDRESS REGISTER ( PBER ) ( Offset 33h-30h ) 0000000 Expansion ROM Base Address ( upper 21 bit ) Address Decode Enable bit 0 : Address Decode Enable, decoding will be enabled if only both enable bit in PFCS<1> and this expansion ROM register are 1. bit 10 - 1 : not used bit 31 - 11 : Defines the upper 21 bits of expansion ROM base address. 10 INDEX MX98713A 5.1.7 INTERRUPT REGISTER ( PFIT ) ( Offset 3Fh-3Ch ) Max_Lat Min-Gnt Interrupt Pin Interrupt Line bit 7 - 0 : Interrupt Pin, fixed to 01h which use INTA#. bit 15 - 8 : Interrupt Line, system BIOS will writes the routing information into this field, driver can use this information to determine priority and interrupt vector. bit 31 - 24 : Max_Lat which is a maximum period for a access to PCI bus. bit 23 - 16 : Min_Gnt which is the maximum period that MX9713A needs to finish a brust PCI cycle. 5.1.8 PCI DRIVER AREA REGISTER ( PFDA ) ( 43h-40h ) Sleep Mode Board Type Driver Special Use bit 31 : Sleep Mode, set to sleep mode which allows access to PCI configuration space, a hardware reset or reset to this bit can exit from sleep mode. Magic packet can be received under sleep mode if CSR16<22> ( Magic Packet Enable ) is set. bit 30 : not used bit 29 : board type bit 15 - 8 : driver is free to read and write this field for any purpose. bit 7 - 0 : not used. 11 INDEX MX98713A 5.2 HOST INTERFACE REGISTERS MX98713A CSRs are located in the host I/O or memory address space. The CSRs are double word aligned and 32 bits long. Definitions and address for all CSRs are as follows : CSR Mapping Register Meaning Offset from CSR Base Address ( PBIO and PBMA ) 00h 08h 10h 18h 20h 28h 30h 38h 40h 48h 50h 58h 60h 68h 70h 78h 80h CSR0 CSR1 CSR2 CSR3 CSR4 CSR5 CSR6 CSR7 CSR8 CSR9 CSR10 CSR11 CSR12 CSR13 CSR14 CSR15 CSR16 Bus mode Transmit poll demand Receive poll demand Receive list demand transmit list base address Interrupt status Operation mode Interrupt enable Missed frame counter Serial ROM and MII management reserved General Purpose timer 10 Base-T status port SIA Reset Register 10 Base-T control port Watchdog timer Magic Packet Register ------------------------------------------------------------------------------------------------------------------------------------------- 12 INDEX MX98713A 5.2.1 BUS MODE REGISTER ( CSR0 ) 0 TAP - Transmit Automatic Polling ZERO - Must be zero CAL - Cache Alignment PBL - Programmable Burst Length BLE - Big/Little Endian DSL - Descriptor Skip Length BAR - Bus Arbitration SWR - Software Reset ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------0 SWR Software Reset, when set, MX98713A resets all internal hardware with the exception of the configuration area and port selection. 1 BAR Internal bus arbitration scheme between receive and transmit processes. The receive channel usually has higher priority over transmit channel when receive FIFO is partially full to a threshold. This threshold can be selected by programming this bit. Set for lower threshold, reset for normal threshold. 6:2 DSL Descriptor Skip Length, specifies the number of longwords to skip between two descriptors. 7 BLE Big/Little Endian, set for big endian byte ordering mode, reset for little endian byte ordering mode, this option only applies to data buffers 13:8 PBL Programmable Burst Length, specifies the maximum number of longwords tobe transferred in one DMA transaction. default is 0, possible values can be 1,2,4,8,16, and 32. 15:14 CAL Cache Alignment, programmable address boundaries of data burst stop, MX98713A can handle non-cache-aligned fragement as well as cache-aligned fragment efficiently. 18:17 TAP Transmit Auto-Polling time interval, defines the time interval for MX98713A to performs transmit poll command automatically at transmit suspended state. ------------------------------------------------------------------------------------------------------------------------------------------- 13 INDEX MX98713A TABLE 5.2.0 TRANSMIT AUTO POLLING BITS ------------------------------------------------------------------------------------------------------------------------------------------CSR<18:17> Time Interval ------------------------------------------------------------------------------------------------------------------------------------------00 No transmit auto-polling, a write to CSR1 is required to poll 01 10 auto-poll every 200 us auto-poll every 800 us 11 auto-poll every 1.6 ms ------------------------------------------------------------------------------------------------------------------------------------------- 5.2.2 TRANSMIT POLL COMMAND ( CSR1 ) Transmit Poll command ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------31:0 TPC Write only, when written with any value, MX98713A read transmit descriptor list in host memory pointed by CSR4 and processes the list. ------------------------------------------------------------------------------------------------------------------------------------------- 14 INDEX MX98713A 5.2.3 RECEIVE POLL COMMAND ( CSR2 ) Receive Poll command ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------31:0 RPC Write only, when written with any value, MX98713A read receive descriptor list in host memory pointed by CSR4 and processes the list. ------------------------------------------------------------------------------------------------------------------------------------------- 5.2.4 DESCRIPTOR LIST ADDRESS ( CSR3, CSR4 ) CSR3 Receive List Base Address Start of Receive List Address CSR4 Transmit List Base Address Start of Transmit List Address 15 INDEX MX98713A 5.2.5 STATUS REGISTER ( CSR5 ) MPI- Magic Packet Interrupt LC- Link Change EB- Error Bits TS- Transmit Process State RS- Receive Process State NIS- Normal Interrupt Summary AIS- Abnormal Interrupt Summary ERI- Early Receive Interrupt FBE- Fatal Bus Error LF- Link Fail GTE- General Purpose Timer Expired ETI- Early Transmit Interrupt RWT-Receive Watchdog Timeout RPS- Receive Process Stopped RU- Receive Buffer Unavailable RI- Receive Interrupt LPANCI- Link Pass/Autonegotiation Completed Interrupt UNF-Transmit Underflow TJT- Transmit Jabber Timeout TU- Transmit Buffer Unavailable TPS- Transmit Process Stopped TI- Transmit Interrupt ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------28 MPI Magic packet received interrupt. Valid only if CSR16<22> bit is set. 27 LC 100 Base-TX link status has changed either from pass to fail or fail to pass. Read CSR12<1> for 100 Base-TX link status. 25:23 EB Error Bits, read only, indicating the type of error that casued fatal bus error. 22:20 TS Transmit Process State, read only bits indicating the state of transmit process. 19:17 RS Receive Process State, read only bits indicating the state of receive process. 16 NIS Normal Interrupt Summary, is the logical OR of CSR5<0>, CSR5<2> and CSR5<6> and CSR5<28>. 15 AIS Abnormal Interrupt Summary, is the logical OR of CSR5<1>, CSR5<3>, CSR5<5>, CSR5<7>, CSR5<8>, CSR5<9>, CAR5,10>, CSR5<11> and CSR5<13>, CSR5<27> 16 INDEX MX98713A Early receive interrupt, indicating the first buffer has been filled in ring mode, or 64 bytes has been received in chain mode. 13 FBE Fatal Bus Error, indicating a system error occured, MX98713A will disable all bus access. 12 LF Link Fail, indicates a link fail state in 10 Base-T port. This bit is valid only when CSR6<18>=0, CSR14<8>=1, and CSR13<3>=0. 11 GTE General Purpose Timer Expired, indicating CSR11 counter has expired. 10 ETI Early Transmit Interrupt, indicating the packet to be transmitted was fully transferred to internal TX FIFO. CSR5<0> will automatically clears this bit. 9 RWT Receive Watchdog Timeout, reflects the network line status where receive watchdog timer has expired while the other node is still active on the network. 8 RPS Write only, when written with any value, MX98713A reads receive descriptor list in host memory pointed by CSR4 and processes the list. 7 RU Receive Buffer Unavailable, the receive process is suspended due to the next descriptor in the receive list is owned by host. If no receive poll command is issued, the reception process resumes when the next recognized incoming frame is received 6 RI Receive Interrupt, indicating the completion of a frame reception. 5 UNF Transmit Underflow, indicating transmit FIFO has run empty before the completion of a packet transmission. 4 LPANCI When autonegotiation is not enabled ( CSR14<7>=0 ), this bit indicates that the 10 Base-T link integrity test has completed successfully. After the link was down, this bit is also set as a result of writing 0 to CSR14<12> ( Link Test Enable ). When Autonegotiation is enabled ( CSR14<7> =1 ) , this bit indicates that the autonegotiation has completed ( CSR12<14:12>=5 ). CSR12 should then be read for a link status report. This bit is only valid when CSR6<18>=0, i.e. 10 Base-T port is selected Link Fail interrupt ( CSR5<12> ) will automatically clear this bit. 3 TJT Transmit Jabber Timeout, indicating the MX98713A has been excessively active. The transmit process is aborted and placed in the stopped state. TDES0<1> is also set. 2 TU Transmit Buffer Unavailable, transmit process is suspended due to the next descriptor in the transmit list is owned by host. 1 TPS Transmit Process Stopped. 0 TI Transmit Interrupt. indicating a frame transmission was completed. ------------------------------------------------------------------------------------------------------------------------------------------14 ERI 17 INDEX MX98713A TABLE 5.2.1 FATAL BUS ERROR BITS ------------------------------------------------------------------------------------------------------------------------------------------CSR5<25:23> Process State ------------------------------------------------------------------------------------------------------------------------------------------000 parity error for either SERR# or PERR#, cleared by software reset. 001 master abort 010 target abort 011 reserved 1XX reserved ------------------------------------------------------------------------------------------------------------------------------------------- TABLE 5.2.2 TRANSMIT PROCESS STATE ------------------------------------------------------------------------------------------------------------------------------------------CSR5<22:20> Process State ------------------------------------------------------------------------------------------------------------------------------------------000 stopped- reset or transmit jabber expired. 001 fetching transmit descriptor 010 waiting for end of transmission 011 filling transmit FIFO 100 reserved 101 Setup packet 110 Suspended, either FIFO underflow or unavailable transmit descriptor 111 closing transmit descriptor ------------------------------------------------------------------------------------------------------------------------------------------- TABLE 5.2.3 RECEIVE PROCESS STATE ------------------------------------------------------------------------------------------------------------------------------------------CSR5<19:17> Process State ------------------------------------------------------------------------------------------------------------------------------------------000 stopped- reset or stop receive command fetching receive descriptor 010 checking for end of receive packet 011 waiting for receive packet 100 suspended, receive buffer unavailable 101 closing receive descriptor 110 Purging the current frame from the receive FIFO due to unavailable receive buffer 111 queuing the receive frame from the receive FIFO into host receive buffer ------------------------------------------------------------------------------------------------------------------------------------------- 18 INDEX MX98713A 5.2.6 OPERATION MODE REGISTER ( CSR6 ) SCR- Scrambler Mode PCS- PCS function TTM- Transmit Threshold Mode SF- Store and Forward HBD- Heartbeat Disable PS- Port Select COE- Collision Offset Enable TR- Threshold Control Bits ST- Start/Stop Transmission Command FC- Force collision mode LOM- Loopback Operation Mode FD- Full Duplex Mode PM- Pass All Multicast PR- Promiscuous Mode SB- Start/Stop Backoff Counter IF- Inverse Filtering PB- Pass Bad Frame HO- Hash-Only Filtering Mode SR- Start/Stop Receive HP- Hash/Perfect Receive Filtering Mode ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------24 SCR Scrambler Mode, default is set to enable scrambler function. Not affected by software reset. 23 PCS Default is set to enable PCS functions. CSR6<18> must be set in order to operate in symbol mode. 22 TTM Transmit Threshold Mode, set for 10 Base-T and reset for 100 Base-TX. 21 SF Store and Forward, when set, transmission starts only if a full packet is in transmit FIFO. the threshold values defined in CSR6<15:14> are ignored 19 HBD Heartbeat Disable, set to disable SQE function in 10 Base-T mode. 18 PS Port Select, deafult is o which is 10 Base-T mode, set for 100 Base-TX mode. A software reset does not affect this bit. 17 COE Collision Offset Enable, set to enable a modified backoff algorithm during low collision situation, reset for normal backoff algorithm. 15:14 TR Threshold Control Bits, these bits controls the selected threshold level for MX98713A's transmit FIFO, transmission starts when frame size within the transmit FIFO is larger than the selected threshold. Full frames with a length less than the threshold are also 19 INDEX MX98713A transmitted. Start/Stop Transmission Command, set to place transmission process in running state and will try to transmit current descriptor in transmit list. When reset, transmit process is placed in stop state. 12 FC Force Collision Mode, used in collision logic test in internal loopback mode, set to force collision during next transmission attempt. This can result in excessive collision reported in TDES0<8> if 16 or more collision. 11:10 LOM Loopback Operation Mode, see table. 9 FD Full-Duplex Mode, set for simultaneous transmit and receive operation, heartbeat check is disabled, TDES0<7> should be ignored, and internal loopback is not allowed. This bit controls the value of bit 6 of link code word . 7 PM Pass All Multicast, set to accept all incoming frames with a multicast destination address are received. Incoming frames with physical address are filtered according to the CSR6<0> bit. 6 PR Promiscuous Mode, any incoming valid frames are accepted, default is reset and not affected by software reset. 5 SB Start/Stop Backoff Counter, when reset, the backoff timer is not affected by the network carrier activity. Otherwise, timer will start counting when carrier drops. 4 IF Inverse Filtering, read only bit, set to operate in inverse filtering mode, only valid during perfect filtering mode. 3 PB Pass Bad Frames, set to pass bad frame mode, all incoming frames passed the address filtering are accepted including runt frames, collided fragments, truncated frames caused by FIFO overflow. 2 HO Hash-Only Filtering Mode , read only bit, set to operate in imperfect filtering mode for both physical and multicast addresses. 1 SR Start/Stop Receive, set to place receive process in running state where descriptor acquisition is attempted from current position in the receive list. Reset to place the receive process in stop state. 0 HP Hash/Perfect Receive Filtering Mode, read only bit, set to use hash table to filter multicast incoming frames. If CSR6<2> is also set, then the physical addresses are imperfect address filtered too. If CSR6<2> is reset, then physical addresses are perfect address filtered, according to a single physical address as specified in setup frame. ------------------------------------------------------------------------------------------------------------------------------------------13 ST TABLE 5.2.4 TRANSMIT THRESHOLD ------------------------------------------------------------------------------------------------------------------------------------------CSR6<21> CSR6<15:14> CSR6<22>=0 CSR6<22>=1 (Threshold bytes) (for 100 Base-TX) (for 10 Base-T) ------------------------------------------------------------------------------------------------------------------------------------------0 00 128 72 20 INDEX MX98713A 0 01 256 96 0 10 512 128 0 11 1024 160 1 XX ( Store and Forward ) ------------------------------------------------------------------------------------------------------------------------------------------- TABLE 5.2.5 DATA PORT SELECTION ------------------------------------------------------------------------------------------------------------------------------------------CSR14<7> CSR6<18> CSR6<22> CSR6<23> CSR6<24> Port ------------------------------------------------------------------------------------------------------------------------------------------1 0 X X X Nway Auto-negociation 0 0 1 X X 10 Base-T 0 1 0 1 1 100 Base-TX ------------------------------------------------------------------------------------------------------------------------------------------- TABLE 5.2.6 LOOPBACK OPERATION MODE ------------------------------------------------------------------------------------------------------------------------------------------CSR6<11:10> Operation Mode ------------------------------------------------------------------------------------------------------------------------------------------00 Normal 01 Internal loopback at FIFO port 11 Internal loopback at the PHY level 10 External loopback at the PMD level ------------------------------------------------------------------------------------------------------------------------------------------- TABLE 5.2.7 FILTERING MODE ------------------------------------------------------------------------------------------------------------------------------------------CSR6<7> CSR6<6> CSR6<4> CSR6<2> CSR6<0> Filtering Mode ------------------------------------------------------------------------------------------------------------------------------------------0 0 0 0 0 16 perfect filtering 0 0 0 0 1 512-bit hash + 1 perfect filtering 0 0 0 1 1 512-bit hash for multicast and physical addresses 0 0 1 0 0 Inverse filtering X 1 0 0 X Promiscuous 0 1 0 1 1 Promiscuous 1 0 0 0 X Pass All Multicast 1 0 0 1 1 Pass All Multicast ------------------------------------------------------------------------------------------------------------------------------------------- 21 INDEX MX98713A 5.2.7 INTERRUPT MASK REGISTER ( CSR7 ) MPIEMagic Packet Interrupt Enable LCE- Link Changed Enable NIE- Normal Interrupt Summary Enable AIE-Abnormal Interrupt Summary Enable ERIE-Early Receive Interrupt Enable FBE- Fatal Bus Error Enable LFE- Link Fail Enable GPTE- General-Purpose Timer Enable ETIE- Early Transmit Interrupt Enable RWE- Receive Watchdog Enable RSE- Receive Stopped Enable RUE- Receive Buffer Unavailable Enable RIE- Receive Interrupt Enable UNE- Underflow Interrupt Enable LPANCIE-Link Pass/Nway Complete Interrupt Enable TJE- Transmit Jabber Timeout Enable TUE- Transmit Buffer Unavailable Enable TSE- Transmit Stopped Enable TIE- Transmit Interrupt Enable ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------28 MPIE Magic Packet Interrupt Enable, enables CSR5<28>. 27 LCE Link Changed Enable, enables CSR5<27>. 16 NIE Normal Interrupt Summary Enable, set to enable CSR5<0>, CSR5<2>, CSR5<6>. 15 AIE Abnormal Interrupt Summary enable, set to enbale CSR5<1>, CSR5<3>, CSR5<5>, CSR5<7>, CSR5<8>, CSR5<9>, CSR5<11> and CSR5<13>. 14 ERIE Early Receive Interrupt Enable 13 FBE Fatal Bus Error Enable, set together with with CSR7<15> enables CSR5<13>. 12 LFE Link Fail Interrupt Enable, enables CSR5<12> 11 GPTE General_-Purpose Timer Enable, set together with CSr7<15> enables CSR5<11>. 10 ETIE Early Transmit Interrupt Enable, enables CSR5<10> 9 RWE Receive Watchdog Timeout Enable, set together with CSR7<15> enables CSR5<9>. 8 RSE Receive Stopped Enable, set together with CSR7<15> enables CSR5<8>. 22 INDEX MX98713A 7 Receive Buffer Unavailable Enable, set together with CSR7<15> enables CSR5<7>. 6 RIE Receive Interrupt Enable, set together with CSR7<16> enables CSR5<6>. 5 UNE Underflow Interrupt Enable, set together with CSR7<15> enables CSR5<5>. 4 LPANCIE Link Pass/Autonegotiation Completed Interrupt Enable 3 TJE Transmit Jabber Timeout Enable, set together with CSR7<15> enables CSR5<3>. 2 TUE Transmit Buffer Unavailable Enable, set together with CSR7<16> enables CSR5<2>. 1 TSE Transmit Stop Enable, set together with CSR7<15> enables CSR5<1>. 0 TIE Transmit Interrupt Enable, set together with CSR7<16> enables CSr5<0>. ------------------------------------------------------------------------------------------------------------------------------------------RUE 5.2.8 MISSED RAME COUNTER ( CSR8 ) Missed Frame Overflow Missed Frame Counter ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------16 MFO Missed Frame Overflow, set when missed frame counter overflows, reset when CSR8 is read. 15:0 MFC Missed Frame Counter, indicates the number of frames discarded because no host receive descriptors were available. ------------------------------------------------------------------------------------------------------------------------------------------- 23 INDEX MX98713A 5.2.9 NON-VOLATILE MEMORY CONTROL REGISTER ( CSR9 ) RD - Read Operation WR - Write Operation BR - Boot ROM Select SR - Serial ROM Select Data - Boot ROM data or Serial ROM control ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------14 RD Boot ROM read operation when boot ROM is selected. 13 WR Boot ROM write operation when boot ROM is slected. 12 BR Boot ROM Select, set to select boot ROM only if CSR9<11>=0. 11 SR Serial ROM Select, set to select serial ROM for either read or write operation. 7:0 Data If boot ROM is selected ( CSR9<12> is set ), this field contains the data to be read from and written to the boot ROM. If serial ROM is selected , CSR9<3:0> are defined as follows : 3 SDO Serial ROM data out from serial ROM into MX98713A. 2 SDI Serial ROM data input to serial ROM from MX98713A. 1 SCLK Serial clock output to serial ROM. 0 SCS Chip select output to serial ROM. Warning : CSR9<11> and CSR9<12> should be mutually exclusive for correct operations. ------------------------------------------------------------------------------------------------------------------------------------------- 24 INDEX MX98713A 5.2.10 FLASH MEMORY PROGRAMMING ADDRESS REGISTER ( CSR10 ) bit 17:0 = boot ROM address 5.2.11 GENERAL PURPOSE TIMER ( CSR11 ) CON - Continuous Mode Timer Value ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------16 CON When set,the general purpose timer is in continuous operating mode. When reset, the timer is in one-shot mode. 15:0 Timer Value contains the timer value in a cycle time of 204.8us. ------------------------------------------------------------------------------------------------------------------------------------------- 25 INDEX MX98713A 5.2.12 10 BASE-T STATUS PORT ( CSR12 ) LPC - Link Partner's Link Code Word LPN - Link Partner Negotiable ANS - Autonegotiation Arbitration State TRF - Transmit Remote Fault APS - Autopolarity State LS10- Link Status of 10 Base -T LS100 - Link Status of 100 Base-TX * Software reset has no effect on this register ------------------------------------------------------------------------------------------------------------------------------------------Field Name Decription ------------------------------------------------------------------------------------------------------------------------------------------31:16 LPC Link Partner's Link Code Word, where bit 16 is S0 ( selector field bit 0 ) and bit 31 is NP ( Next Page ). Effective only when CSR12<15> is read as a logical 1. the following field. 15 LPN Link Partner Negotiable, set when link partner support NWAY algorithm and CSR14<7> is set. 14:12 ANS Autonegotiation Arbitration State, arbitration states are defined 000 = Autonegotiation disable 001 = Transmit disable 010 = ability detect 011 = Acknowledge detect 100 = Complete acknowledge detect 101 = FLP link good; autonegotiation complete 110 = Link check When autonegotiation is completed, an ANC interrupt ( CSR5<4>) is generated, write 001 into this field can restart the autonegotiation sequence if CSR14<7> is set. Oth 26 INDEX MX98713A erwise, these bits should be 0. Transmit Remote Fault Autopolarity State, set when polarity is positive. When reset, the 10Base-T polarity is negative. The received bit stream is inverted by the receiver. 2 LS10 Set when link status of 10 Base-T port link test fail. Reset when 10 Base-T link test is in pass state. 1 LS100 Link state of 100 Base-TX, this bit reflects the state of SD pin, effective only when CSR6<23>= 1 ( PCS is set ). Set to indicate a fail condition .i.e. SD=0. ------------------------------------------------------------------------------------------------------------------------------------------11 3 TRF APS 5.2.13 SIA RESET REGISTER (CSR13) Nway Reset - Nway and 10 Base-T PHY level reset ------------------------------------------------------------------------------------------------------------------------------------------Field Name Decription ------------------------------------------------------------------------------------------------------------------------------------------0 Nway Reset While writing 0 to this bit, resets the CSR12 & CSR14. ------------------------------------------------------------------------------------------------------------------------------------------- 27 INDEX MX98713A 5.2.14 10 BASE-T CONTROL PORT (CSR14) T4 - 100 Base-T4 ( link code word ) TXF - 100 Base-TX full duplex ( link code word ) TXH - 100 Base-TX half duplex ( link code word ) LTE - Link Test enable RSQ - Receive Squelch Enable ANE - Autonegotiation Enable HDE- Half Duplex Enable PWD10 - Power down 10 Base-T LBK - Loopback ( MCC ) ------------------------------------------------------------------------------------------------------------------------------------------Field Name Decription ------------------------------------------------------------------------------------------------------------------------------------------18 T4 Bit 9 of link code word for T4 mode. 17 TXF Bit 8 of link code word for 100 Base-TX full duplex mode. 16 TXH Bit 7 of link code word for 100 Base-TX half duplex mode. Meaningful only when CSR14<7> ( ANE ) is set. 12 LTE Link Test Enable, when set the 10 Base-T port link test function is enabled. 8 RSQ Receive Squelch Enable for 10 Base-T port. Set to enable. 7 ANE Autonegotiation Enable, . 6 HDE Half-Duplex Enable, this is the bit 5 of link code word, only meaningful when CSR14<7> is set. 2 PWD10 set to power down 10 Base-T module, this will force both TX and RX port into tri-state and prevent AC current path. Reset for normal 10 Base-T operation. 1 LBK Loop back enable for 10 Base-T MCC. ------------------------------------------------------------------------------------------------------------------------------------------- INDEX MX98713A 5.2.15 WATCHDOG TIMER ( CSR15) MBZ - Must Be Zero RWR - Receive Watchdog Release RWD - Receive Watchdog Disable JCK - Jabber Clock HUJ - Host Unjabber JAB - Jabber Disable ------------------------------------------------------------------------------------------------------------------------------------------Field Name Description ------------------------------------------------------------------------------------------------------------------------------------------5 RWR Defines the time interval no carrier from receive watchdog expiration until reenabling the receive channel. When set, the receive watchdog is release 40-48 bit times from the last carrier deassertion. When reset, the receive watchdog is released 16 to 24 bit times from the last carrier deassertion. 4 RWD When set, the receive watchdog counter is disable. When reset, receive carriers longer than 2560 bytes are guaranted to cause the watchdog counter to time out. Packets shorter than 2048 bytes are guaranted to pass. 2 JCK When set, transmission is cut off after a range of 2048 bytes to 2560 bytes is tranmitted. When reset, transmission for the 10 Base-T port is cut off after a range of 26 ms to 33ms. When reset, transmission for the 100 Base-TX port is cut off after a range of 2.6ms to 3.3ms. 1 HUJ Defines the time interval between transmit jabber expiration until reenabling of the transmit channel. When set, the transmit channel is released immediately after the jabber expiration. When reset, the jabber is released 365ms to 420 ms after jabber expiration for 10 Base-T port. When reset, the jabber is released 36.5ms to 42ms after the jabber exporation for 100 Base-TX port. 0 JBD Jabber Disable, set to disable transmit jabber function. ------------------------------------------------------------------------------------------------------------------------------------------- 29 INDEX MX98713A 5.2.16 MAGIC PACKET REGISTER ( CSR16 ) MPE ( Magic Packet Enable ) ------------------------------------------------------------------------------------------------------------------------------------------field Name Description ------------------------------------------------------------------------------------------------------------------------------------------bit 31:23 reserved bit 22 MPE Magic Packet Enable, set to enable Magic Packet Mode bit 21:0 reserved ------------------------------------------------------------------------------------------------------------------------------------------Sleep mode and MPE mode can be used seperately. When Sleep and MPE are both set, the Sleep mode dominate MPE, i.e., no magic packet can be detected since both TX and RX channel are shut off in sleep mode. In both sleep and Magic Packet mode, PWD100B will be asserted low to shut down external 100 Base-TX PHY/PMD chips. On the detection of magic packet, PWD100B pin will be asserted high. 30 INDEX MX98713A 6. AC/DC CHARACTERISTICS 6.1 BOOT ROM AND FLASH TIMING FRAME# AD<31:0> xx add xx xx xx xx xx data xx FCS# T1 BPA<17:0> T2 Valid ROM address Taa FOE# T3 BPD<7:0> FWE# Valid Data T4 T5 8 PCICLK -PCI adddress to FCS# valid delay T1 < 1 PCICLK -BPA address valid to CS# low >= 0 ns -Boot ROM speed grade ( Taa ) <= 8 PCICLK - 15 ns e.g. For 33MHz PCI bus, Taa <= 225ns, T1 <= 90ns -FCS# low till FOE# low (T3) >= 2 PCICLK -FCS# low till FWE# low (T4) >= 0ns -Data valid till FWE# low (T5) >= 0ns 31 INDEX MX98713A 6.2 ABSOLUTE OPERATION CONDITION Supply Voltage (VCC) DC Input Voltage (Vin) DC Output Voltage (Vout) Storage Temperature Range (Tstg) Power Dissipation (PD) Lead Temp. (TL) (Soldering, 10 sec) ESD Rating (Rzap = 1.5k, Czap = 100pF) Clamp Diode Current -0.5V to +7.0V -0.5V to VCC + 0.5V -0.5V to VCC + 0.5V -55oC to +150 oC TBD 260 oC 1.5kV + 20mA - 6.3 DC CHARACTERISTICS Symbol TTL/PCI Input/Output Voh Vol Vih Vil Iin Ioz Minimum High Level Output Voltage Maximum Low Level Output Voltage Minimum High Level Input Voltage Maximum Low Level Input Voltage Input Current Minimum TRI-STATE Output Leakage Current Vi = VCC or GND Vout = VCC or GND - 1.0 -10 Ioh = -3mA Iol = +6mA 2.0 0.8 + 1.0 +10 2.4 0.4 V V V V uA uA Parameter Conditions Min Max Units LED output Driver Vlol LED turn on Output Voltage Iol = 16mA 0.4 V Supply Idd Vdd Average Supply Current Average Supply Voltage CKREF =25MHz PCICLK = 33MHz TBD 4.75V TBD 5.25V mA V 32 INDEX MX98713A 7.0 AC CHARACTERIZATION 7.1 TRANSMIT SIGNAL TIMING: tclkh tclkl TXCLK tdout TXD[3:0] TXEN Symbol tclkh Parameter TXCLK high for 25MHz ( 100 Base-TX ) TXCLK high for 2.5MHz ( 10 Base-T ) Min 14 140 14 140 2 Max 26 260 26 260 25 Units ns ns ns ns ns tclkl TXCLK low for 25MHz ( 100 Base-TX ) TXCLK low for 2.5MHz ( 10 Base-T ) tdout TXD,TXEN to TXCLK rising edge * The duty cycle of the TXCLK signal shall be between 35% and 65% inclusively. 7.2 RECEIVE SIGNNAL TIMING trclkh trclkl RXCLK trxsu trxhd RXD[3:0] RXDV RXER 33 INDEX MX98713A Symbol trclkh** Parameter RXCLK high for 25MHz ( 100 Base-TX ) RXCLK high for 2.5MHz ( 10 Base-T ) trclkl** RXCLK low for 25MHz ( 100 Base-TX ) RXCLK low for 2.5MHz ( 10 Base-T ) trxsu trxhd RXD,RXDV & RXER setup time to RXCLK rising edge RXD,RXDV & RXER hold time to RXCLK rising edge Min 14 140 14 140 10 10 Max 26 260 26 260 Units ns ns ns ns ns ns * The maximun time of 10Base-T is not guaranteed at begginning and end of frame. * The minimun high and low times of RXCLK shall be 35% of the nominal period. 7.3 Management Signal Timing MDIO source by STA(station management entity): tmdch tmdcl MDC tmdsu MDIO tmdhd Symbol tmdch tmdcl tmdsu tmdhd MDC high time MDC low time Parameter Min 200 200 10 10 Max Units ns ns ns ns MDIO to MDC high setup time sourced by STA MDIO to MDC high hold time sourced by STA 34 INDEX MX98713A 7.4 MANAGEMENT SIGNAL TIMING MDIO SOURCE BY PHY: MDC tmdp MDIO Symbol tmdp Parameter MDC high to MDIO data valid Min 2 Max 300 Units ns 7.5 10BASE-T TRANSMIT TIMING (End of Packet) 1 TXP/M 0 0 ttoh 1 TXP/M 0 1 ttol Symbol ttoh ttol Parameter Transmit Output High before Idle (Half Step) Transmit Output Idle Time (Half Step) Min 200 Max Units ns 800 ns 35 INDEX MX98713A 7.6 10BASE-T RECEIVE END OF PACKET TIMING 1 1 teop1 RXP RXM 1 0 teop0 RXP RXM Symbol teop1 teop0 Parameter Receive End of Packet Hold Time after "1" Receive End of Packet Hold time after "0" Min 225 225 Max Units ns ns 7.7 10BASE-T LINK PULSE TIMING tipw tip TXOP TXOM Symbol tip tipw Parameter Time between Link Output Pulses Link Integrity Output Pulse Width Min 8 80 Max 24 130 Units ms ns 36 INDEX MX98713A 7.8 FLP ( Fast Link Pulse ) TIMING: tipw TXOP clock tfpbw TXOP flp Burst tfd tfc data tfpb clock flp Burst Symbol tfd tfc tipw tfpb tfpbw Parameter Flp Clock Pulse to Data Pulse ( Data = 1) Flp Clock Pulse to Clock Pulse Fast Link Output Pulse Width FLP burst to FLP Burst FLP Burst Width Min 58 118 80 12 1.8 Max 65 130 130 18 2.1 Units us us ns ms ms Note: FLP related timing parameters are guranted by design and not measured data on tester. 37 INDEX MX98713A 7.9 SERIAL TRANSMISSION WITH A COLLISION DETECT HEARTBEAT TIMING txcl SR7_TXC txcenh SR7_TXE txcksdv SR7_TXD 1 0 1 txcksdh 0 tdcdh SR7_COL cdhw tcdl txcyc tcenl txch Symbol txch txcl txcyc txcenh txcksdv txcksdh tcdl tcenl tdcdh cdhw Transmit Clock High Time Transmit Clock Low Time Parameter Min 36 36 90 Max Units ns ns Transmit Clock Cycle Time Transmit Clock High to Transmt Enable High Transmit Clock High to Serial Data Valid Serial Data Hold Time from Transmit Clock High Transmit Clock to Data Low Transmit Clock to SR7_TXE Low SR7_TXE Low to Start of Collision Dectect Heartbeat Collision Dectect Width 1100 45 65 ns ns ns ns 6 55 55 0 2 64 ns ns txcyc txcyc 38 INDEX MX98713A 7.10 SERIAL RECEIVE TIMING DIAGRAM rxcl rxch SR7_RXC rxcyc SR7_CRS rds pts rdh SR7_RXD 1 0 1 sync tdrb rxrck tcrsl tifg Symbol rxch rxcl rxcyc rds rdh pts rxrck tdrb tifg tcrsl Receive Clock High Time Receive Clock Low Time Receive Clock Cycle Time Parameter Min 36 36 90 20 15 8 3 Max Units ns ns 1100 ns ns ns rxcyc rxcyc Receive Data Setup Time to Receive Clock High Receive Data Hold Time from Receive Clock High First Preamble Bit to Synchronize Minimun Number of Receive Clocks after CRS Low Maximun of Allowed Dribble Bits/Clocks Receive Recovery Time Receive Clock to Carrier Sense Low 5 40 0 1 rxcyc rxcyc rxcyc 39 INDEX MX98713A 7.11 SERIAL TRANSMIT TIMING DIAGRAM TXC tcdl TXE tjam TXD tcdj JAM1 JAM32 COL tcolw Symbol tcolw tcdj tjam Parameter Collision Detect Width Delay From Collision to First Bit of JAM (Note 1) JAM Period (Note 2) Min 2 Max Units txcyc cycles 8 32 txcyc cycles txcyc cycles Note 1 : The NIC must synchronize to collision detect. If the NIC is in the middle of serializing a byte of data the remainder of the byte will be serialized. Thus the jam pattern will start anywhere from 1 to 8 TXC cycles after COL is asserted. Note 2 : The NIC always issues 32 bits of jam. The jam is all 1's data. 40 INDEX MX98713A 8.0 PACKAGE INFORMATION 160-PIN PLASTIC QUAD FLAT PACK 41 INDEX MX98713A MACRONIX INTERNATIONAL CO., LTD. HEADQUARTERS: No.3, Creation Road III, Science-Based Industrial Park, Hsin Chu, Taiwan, R.O.C. TEL:+886-3-578-8888 FAX:+886-3-578-8887 TAIPEI OFFICE: 12F, No.4, Min-Chuan E.Rd., Sec 3, Taipei, Taiwan, R.O.C. TEL:+886-3-509-3300 FAX:+886-3-509-2200 EUROPE OFFICE: Koningin Astridlaan 59, Bus 1, 1780 Wemmel, Belgium TEL:+32-2-456-8020 FAX:+32-2-456-8021 SINGAPORE OFFICE: 5 Jalan Masjid Kembangan Court #01-12 Singapore 418924 TEL:+65-747-2309 FAX:+65-748-4090 MACRONIX AMERICA, INC. 1338 Ridder Park Drive, San Jose, CA95131 U.S.A. TEL:+1-408-453-8088 FAX:+1-408-453-8488 JAPAN OFFICE: NFK Kawasaki Building, 8F, 1-2 Higashida-cho, Kawasaki-ku Kawasaki-shi, Kawasaki-ken 210, Japan TEL:+81-44-246-9100 FAX:+81-44-246-9105 MACRONIX INTERNATIONAL CO., LTD. reserves the right to change product and specifications without notice. 42 |
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